A) Field of the Invention
This invention relates to a method for manufacturing an insulated-gate type field effect transistor having an extension drain structure or the likes.
B) Description of the Related Art
An insulated-gate type field effect transistor having a lightly doped drain (LDD) structure is generally well known. The extension drain structure is basically similar to the LDD structure but the extension drain structure can avoid deterioration of performance caused by parasitic resistance by heightening an impurity concentration, in other words, it can restrain a short channel effect by doping ions at lower energy comparing to source and drain regions. Incidentally, a dose amount for the LDD region is about 5×1013 cm−2 at most, as dose amount for the extension drain region is about 1×1014 to 1×1015 cm−2, and a dose amount four the source and drain regions is not less than about 1×1015 cm−2. It is said in common that the LDD structure has been taken over by the extension drain structure since a thickness of a gate electrode (wiring) became about 0.25 μm because the performance deterioration by parasitic resistance in the LDD part became unable to be overlooked.
Conventionally a method for manufacturing an insulated-gate type field effect transistor with the LDD structure as shown in FIG. 17 to FIG. 19 is known. The method is disclosed for example in Japanese Laid-open Patent No. H06-275635.
In a process shown in FIG. 17, after forming a field insulating film 2 having element hole 2a on one main surface of a p-type semiconductor substrate 1, a gate insulating film 3 made of silicon oxide or the like is formed on a semiconductor surface of in the element hole 2a. After depositing a poly-silicon layer on the insulating film 3, a gate electrode layer 4 composed of a remaining part of the poly-silicon layer by performing an etching process using a resist layer 5 as a mask. At this time, the gate insulating film 3 under the gate electrode layer 4 is remained whereas other part of the gate insulating film 3 is removed by the etching.
In a process shown in FIG. 18, with covering the gate electrode layer 4 by the resist layer 5, each side edge of the electrode layer 4 is retreated from a side edge of the resist layer for about a distance Δd=0.15 μm by a side etching process. As a result, for example, a width of the electrode layer 4 (a gate width) is reduced to 0.8 μm to 0.5 μm.
In a process shown in FIG. 19, after removing the resist layer 5, an n−-type source region 8 and an n−-type drain region 9 are formed respectively in p-type regions on source side and drain side of the electrode layer 4 by doping phosphorus ions with a mask consisting a lamination of the gate electrode layer 4 and the gate insulating film 3 and the field insulating film 2. The drain region 9 is usually called the LDD region.
An yield of the above-described conventional transistor is low, that is, the resist layer 5 is etched twice in the processes shown in FIG. 17 and FIG. 18 so that it is not easy to control the amount of side etching of the gate electrode layer 4, and amounts of the side etching vary widely. Therefore, gate widths vary widely. Moreover, in the ion doping process in FIG. 17, the ion doping is performed to the semiconductor surface exposed in the element hole 2a; therefore, the doping depths of the ions vary widely due to the so-called channeling phenomenon. By that, depths of n+-type regions also vary widely.
In addition to that, a total of two ion doping processes is necessary in the source and drain formation process in FIG. 17 and the LDD formation process in FIG. 19; therefore, the number of processes is large, and low energy ion doping apparatus is necessary for the LDD formation process in FIG. 19.